MST™ CMOS is an ultra-thin film of reengineered silicon that improves the conductive “channel” in a transistor.

It is based on an engineered silicon lattice structure that has unique electrical properties. These properties address a number of key device engineering challenges the industry currently faces as it tries to move forward with smaller geometries.

The Company believes MST™ CMOS will be of substantial value to the Semiconductor Industry in its quest to extend the CMOS roadmap, delivering multiple scaling benefits through a single technology that requires relatively minor modifications to the industry standard CMOS manufacturing flow.

One Film...Many Benefits

The ability to manipulate the electrical properties of silicon through the Company’s proprietary MEARS Silicon Technology has far‐reaching impact. Our breakthrough MST™ CMOS technology delivers multiple, simultaneous benefits for both nMOS and pMOS devices using a single film insertion.

Increased Mobility

Improved in‐plane carrier transport leads to increased transconductance and drive current. These benefits are believed to be applicable to a variety of IC types including microprocessors, DRAM, SRAM, flash, and other memory ICs, and RF and mixed‐signal devices. Drive and effective current increases of 10%-20% and improved mobility at high and low fields have already been demonstrated during third party evaluations. The performance improvements can also be traded-off for reduced static power, typically providing up to a 60% static power reduction.

Reduced Leakage

Gate leakage reduction of up to 50% by impeding unwanted current flow in the vertical direction has already been demonstrated during third party evaluations.

Reduced Variability

The improved channel doping – a more ordered, steep retrograde well/channel profile – delivers additional and increasingly important benefits in the form of Vt variability reduction and improved matching. More than a 50% reduction in Vt variability and improved transistor matching has already been demonstrated during third party evaluations.

‘Silicon‐on‐Silicon’ – Additive Benefits

MST™ CMOS is a ‘Silicon‐on‐Silicon’ solution that provides multiple benefits through a single and relatively simple modification to the standard CMOS manufacturing flow; one that can be used across multiple product categories and generations. The Company believes that quick and widespread MST™ CMOS adoption should be possible once it is accepted as a proven solution, even more so since it can be combined with other scaling and enhancement technologies already in use such as Strain, SOI, HKMG, and finFETs and used to add to and extend their benefits. Additive benefits of MST™ CMOS combined with Strain and SOI techniques have already been demonstrated during third party evaluations.

High Benefit / Cost Ratio

MST™ CMOS lends itself to further enhancement and customization, as the epitaxial layer design can be optimized for specific applications based on performance priorities and cost targets. With a low fabrication process flow cost for the single film insertion, MST™ CMOS delivers a high benefit to cost ratio across multiple products.

Fab Life Extension

Measured as a cost adder per wafer, MST™ CMOS provides a stronger value proposition than the leading enhancement and scaling options (including stress memorization, eSiGe, Dual Stress Liner, SOI, and HKMG). The MST™ CMOS technology offers a more compelling and cost effective alternative to device manufacturers that have not yet transitioned to more leading edge technologies and are looking to extend the life of their current fabrication infrastructure.